Verilator syntax support boundaries, measured: what Verilog/SystemVerilog runs and what fails silently

The short answer

Verilator 5.052 covers far more than “synthesizable RTL”: delays, real arithmetic, open-drain pullup/nmos, tri-state and SVA work. It lacks gate-level precision; its worst failures are silent.

How this was established: the same source was given to Verilator 5.052 and VCS 2023.12 for A/B comparison; the support matrix comes from 39 standalone cases (one file per construct), each linted, built and run — not copied out of documentation.

Environment and method

What a real design needed changed (brief)

Subject: a 1080p timing controller on a 7-series FPGA, 29 modules, 100 MHz input, 490 MHz LVDS serial output, I2C slave; the testbench runs 43 ms of simulation time.

Four changes are mandatory:

Result: the two BMP frames the TB dumps are byte-identical to the VCS run (same md5), and the end time agrees to 1 ps; build 4.6 s (-j32) against 23 s for VCS, simulation 52 s against 51 s.

Syntax support matrix (measured)

Fully supported, and identical to VCS

Two conclusions that go against older folklore, both settled by measurement:

• disable {named fork} is supported. fork: W ... join_any; disable W; leaves only the winning branch printing; disable fork works as well.
• SVA is not merely parsed. On a violation it really prints %Error: Assertion failed ... %Error: Verilog $stop and aborts the simulation — treat that as a failure in CI.

Not supported (hard error)

Accepted but silently wrong (the class to watch)

On --timing: 5.x has it on by default, so not passing it gives the same result; what you must guard against is turning it off (or +notimingchecks, which is “accepted and ignored”). Write --timing explicitly in the script anyway, so the intent stays on the command line.

Waveform pitfalls

1. $dumpvars needs --trace (VCD) or --trace-fst (FST) at build time. Without that compile-time switch $dump* is a silent no-op: the run finishes with no file and no message.
2. $dumpoff/$dumpon do nothing (see the table above), so “dump only one window” is impossible; the only knob is the level argument of $dumpvars(level, scope).
3. Three orders of magnitude in size: for the same 43 ms design with two 490 MHz buses, dumping only the TB and the DUT top level — VCD 12.4 GB, FST 123 MB. There is no equivalent of Verdi’s suppress, so the only levers are scope level or FST.
4. Dumping is itself the main cost: same configuration, 52 s with no waveform, 152 s with FST (about 3x), about 98 s with VCD; on the VCS side enabling FSDB adds 0 s. If you want speed, do not dump by default.
5. Verdi cannot read FST, GTKWave reads it natively; building FST support also needs the lz4 headers (fst2vcd converts to VCD for other tools).
6. $time returns an integer number of time units: in a 1 ns/1 ps design a %0t print shows 42922750.000 ns, which looks 355 ps worse than VCS, while the last timestamp in the VCD is 42922749645 ps — the two agree. Judge the time axis from the waveform timestamps, not from the $time print.

Rules when writing TB / RTL (checklist)

1. Do not start a comment with // Verilator. Verilator treats // verilator ... as a pragma and fails with %Error-BADVLTPRAGMA: Unknown verilator comment. Use a prefix such as // NOTE: or // VLNOTE:.
2. Check whether a behavioural model of the primitive exists. An IP available only as encrypted secureip is a dead end; where a fast behavioural model exists, functional simulation is fully adequate.
3. An XMR into a global (such as glbl.GSR) needs the right instance name: write glbl glbl(); in the testbench (instance named like the module); Verilator resolves it by searching upward.
4. -Wno-fatal must come with warning triage. Grep the UNSUPPORTED / SPECIFYIGN / STMTDLY / WIDTHEXPAND / MULTIDRIVEN codes out and judge each one; using -Wno-fatal as “zero warnings” lets the silent distortions through.
5. A failing assertion $stops the simulation, so a regression script must treat it as a failure in both exit code and log matching, not as “the run finished”.
6. Do not rely on drive strength or gate delays. The common open-drain plus pull-up topology (“strong0 overrides pull1”) comes out right, but “pull1 overrides weak0” is wrong, and there is no warning.
7. Run --lint-only --timing before building: clearing the syntax problems in the lint stage is much faster than trying again with a 4 s compile each time.
8. Give the dump only the levels you need: $dumpvars(1, tb) plus $dumpvars(1, dut) is usually enough to locate a problem; dumping the whole hierarchy costs an unreasonable amount of size and time.

When not to use Verilator

How to reproduce

One case per construct, one file each, lint first and build second:

# a single construct
verilator --lint-only --timing -Wno-fatal --top-module m case.sv
# the suspicious ones (assertions / coverage / process control) really run
verilator --binary --timing -Wno-fatal --coverage --top-module m -o V case.sv && ./obj_dir/V
# coverage summary (reports covergroup hit rates)
verilator_coverage coverage.dat

To check “does it agree with the commercial simulator”, give the same file to both simulators and compare the printed times and values (every “identical / different” in this note comes from doing exactly that).

Limitations

The data here comes from a single Verilator version (5.052), 39 syntax cases and one real design of 29 modules, so it does not describe how earlier or later versions behave; program, clocking blocks and DPI-C were only proven to parse/build, their runtime semantics were not checked case by case. Re-run the lint matrix after upgrading Verilator.